Abstract
A systematic approach for designing systolic arrays with concurrent error detection (CED) capability using time and/or space redundancy is proposed. This approach is based on a new theory which relates CED and the generalized space-time mapping. Under a restriction that there is one generated (modified) variable in the systolic arrays, a simplified CED scheme is presented. That not only significantly reduces the hardware and time overheads but also has capability of error correction. As well, the resulting systolic array can be used to compute two problem instances simultaneously to achieve double throughput without extra cost.
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