A system verification environment for mixed-signal SOC design based on IP bus

Abstract

A reusable SoC verification environment is presented in this paper. This versatile environment, which is based on VSI Alliance IP bus standard, is in accordance with pervasive rules of IP reusing, and hence is suitable for varieties of designs. Through collaborating with other EDA tools, the environment has powerful capability to support HW/SW co-simulation and digital/analog co-simulation. To be user friendly, the environment is well organized to accommodate new IPs easily. It is configurable for verifications from system-level prototyping to gate level simulation. This environment works well for verifications of digital, analog and mixed-signal SoC designs.