Abstract
Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of the filters that remove the distortion of the data. Nevertheless, a part of the available bandwidth has to be destined to these symbols. Until now, no alternative solution has demonstrated to be fully satisfying for commercial use, but one technique that looks promising is superimposed training (ST). This work describes a hybrid software‐hardware FPGA implementation of a recent algorithm that belongs to the ST family, known as Data‐dependent Superimposed Training (DDST), which does not need extra bandwidth for its training sequences (TS) as it adds them arithmetically to the data. DDST also adds a third sequence known as data‐dependent sequence, that destroys the interference caused by the data over the TS. As DDST′s computational burden is too high for the commercial processors used in mobile systems, a System on a Programmable Chip (SOPC) approach is used in order to solve the problem.
Highlights
The air is inherently noisy and its nature can contribute to the presence of different kinds of interference, as the one known as Intersymbol Interference or ISI, in which the energy of the message symbols is spread in such way that a part of each symbol overlaps with that of the neighboring symbols
The most extended technique to integrate the training sequences to the information is known as time-division multiplexed channel estimation or time-division multiplexed training (TDMT), where some of the transmission slots are used for the pilots or training symbols [1]
As this work presents the first implementation of the Datadependent Superimposed Training (DDST) channel estimation algorithm on an FPGA, a hybrid software/hardware implementation presents the advantage of a simple control through a series of software coded instruction and the power of dedicated hardware coprocessors to perform the most time and resources demanding tasks of the DDST receiver stages for the obtaining of the estimate
Summary
The air is inherently noisy and its nature can contribute to the presence of different kinds of interference, as the one known as Intersymbol Interference or ISI, in which the energy of the message symbols is spread in such way that a part of each symbol overlaps with that of the neighboring symbols. This channel can be modeled as a linear system, whose effects can be reverted in the receiver, if one knows its parameters with enough precision To obtain these parameters, the majority of the digital wireless communication systems use sequences of known symbols that are called training sequences. The most extended technique to integrate the training sequences to the information is known as time-division multiplexed channel estimation or time-division multiplexed training (TDMT), where some of the transmission slots are used for the pilots or training symbols [1] The performance of this approach is very high, but it has the disadvantage of needing part of the available bandwidth to accommodate the extra data. As this work presents the first implementation of the DDST channel estimation algorithm on an FPGA, a hybrid software/hardware implementation presents the advantage of a simple control through a series of software coded instruction and the power of dedicated hardware coprocessors to perform the most time and resources demanding tasks of the DDST receiver stages for the obtaining of the estimate
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