A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design

Abstract

Nowadays, processor micro-architectures are becoming more and more complex. Consequently, designers increasingly need powerful abstraction and structuration mechanisms, as well as design methodologies that automatically and formally derive low-level concrete designs from high-level abstract ones. In this context, this paper proposes a methodology for RISC processor micro-architecture design. The proposed methodology uses mainly SysML to model both ISA and MA levels and the functional language CLEAN to describe them. Functional specifications in CLEAN are automatically generated from the ISA and MA models. These specifications, which are executable and formally verifiable, are used for simulation and verification. The proposed approach is validated by a case study that consists of designing the micro-architecture of MIPS processor. It shows how to easily model and generate CLEAN specifications describing the ISA and MA levels. It also illustrates, with multiple cases, how the generated specifications are used to simulate the MA. The results of the simulation phase prove the efficiency of the proposed modeling and code generation techniques.