A survey of power management techniques for phase change memory

Abstract

The demands of larger memory capacity in high-performance computing systems have motivated the researchers to explore alternatives of dynamic random access memory (DRAM). Since phase change memory (PCM) provides high-density, good scalability and non-volatile data storage, it has received significant amount of attention in recent years. A crucial bottleneck in wide-spread adoption of PCM, however, is that its write latency and energy are very high. Recently, several architecture and system-level techniques have been proposed to address this issue. In this paper, we survey several techniques for managing power consumption of PCM. We also classify these techniques based on their characteristics to highlight their similarities and differences. The aim of this paper is to provide insights to researchers into working of PCM power-management techniques and also motivate them to propose even better techniques for designing future 'green' PCM-based main memory systems.