A surface-potential-based drain current model suitable for poly-Si thin film transistors with thin body and thin gate oxide

Abstract

Polycrystalline silicon thin film transistors with thin body and thin gate oxide can realize high performance and relative low power consumption simultaneously. Considering their wide applications, a surface-potential-based drain current model suitable for devices with the above structure is derived on charge sheet approximation considering the double exponential trap state distribution, the interface charge and the effect of the back surface potential. According to the calculated areal density of the charges under the gate oxide, the ionized acceptors and the trapped charges, the areal density of the inversion charge is obtained. Under several mathematical treatments, a surface-potential-based drain current model suitable for devices with thin body and thin gate oxide is developed accompanying the quantitative model-validity conditions for low and high state densities respectively. Under high and low state densities respectively, this proposed surface-potential-based drain current model is verified by 2D-device simulation in devices’ transfer characteristics under various drain biases in the situations without or with interface charge.