Abstract
A digital shift register using the surface-charge transistor structure in which adjacent rows propagate in opposite directions and which has refresh turn-around circuits at the ends of each row is described. Two process compatible refresh circuits requiring only four times the basic bit storage area have been designed, and a test circuit composed of two 16-bit shift registers that propagate in opposite directions and are connected by these circuits has been built and tested. The regeneration characteristics of these refresh circuits have been measured as a function of transfer time in both the complete and partial transfer modes (`fat zero'). Operation of one of these 32-stage shift registers and its refresh at 10 MHz is presented.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
