A Supply-Noise-Insensitive PLL in Monolithic Active Pixel Sensors

Abstract

A high-performance CMOS charge pump supply-noise-insensitive phase-locked loop (SNI-PLL) for on-chip clock generation of Monolithic Active Pixel Sensors (MAPS) is presented. The SNI-PLL employs a voltage regulator which provides two stable power supplies to the charge pump and the voltage-controlled oscillator (VCO), respectively. The voltage regulator achieves a Power Supply Noise Rejection (PSNR) of -40 dB over the entire frequency spectrum by using virtual grounded cascode compensation technique. The presented SNI-PLL generates a 160 MHz clock with a Time Interval Error (TIE) of 0.062 UI (Unit Interval) from a 10 MHz reference clock in a noisy power supply environment. The circuit was fabricated with a 0.35 μ m standard CMOS process and occupies 0.38 mm 2 area. The power consumption of the SNI-PLL is about 15.2 mW at 160 MHz.