Abstract
A superconductive ring-pipelined network system is proposed to improve performance of multi-processor systems, and a prototype chip is designed. A throughput of a data exchange between processor elements limits the effective performance of the multi-processor systems. The features of the superconductive ring-pipelined network system are a high-clock-frequency operation by using high-speed Josephson gates and wide band superconductive transmission lines, and a high-density package because of its low power consumption. These advantages significantly reduce pipeline loss and improve flexibility in data exchange. Therefore, this network system is capable of improving the overall effective performance of multiprocessor systems. The prototype chip consists of three Josephson ring interface circuits and superconductive interconnections positioned in between these interface circuits. There are a total 1,130 gates. The prototype chip is designed to be operated up to a clock frequency of 10 GHz. Therefore, the total system throughput is estimated to be 60 Gbps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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