Abstract

A fully integrated successive-approximation (SAR) switched-capacitor (SC) DC-DC converter is presented that overcomes the coarse output voltage resolution limitation of traditional SC converters. An SAR SC converter cascades multiple stages of 2:1 SC converters, and achieves a fine-grained conversion ratio resolution of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> /2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sup> , where V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> is the input voltage and N is the number of stages. As the SAR SC converter generates the output voltage through SAR, each stage of 2:1 SC converter provides a fixed voltage level, requiring minimal configuration change for regulation. Analysis shows that the SAR SC converter has a slow-switching-limit output impedance increasing proportionally to log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (number of resolution), and switching loss of bottom-plate parasitic capacitor decreasing with the number of stages. As a test chip, an SAR SC converter with 7 b resolution is fabricated in 180 nm CMOS process and implemented by cascading 4:1 and five 2:1 two-phase interleaving SC stages. It achieves 31.25 mV voltage resolution with output voltages over 0.4 V at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> = 4 V. Using this fine grain voltage regulation approach, line and load regulations are implemented with a feedback/feedforward controller with peak efficiency of 72% for load currents from 0 to 300 μA. The test chip occupies 1.69 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and utilizes on-chip capacitors of 2.24 nF in total.

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