Abstract
This work presents an amplifier targeting the acquisition of intracranial electroencephalography signals with low power consumption, low voltage supply, low noise, and high common-mode rejection ratio (CMRR). A prototype was designed in a 180 nm FD-SOI CMOS technology and characterized by simulations. It presents an input noise of 3.2 µV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> , a current consumption of 0.5 µA, and it operates from a 1.8 V voltage supply, which represents a power consumption of 0.9 µW. The bandwidth ranges from 0.1 Hz to 1 kHz, the gain is 40 dB, the CMRR is greater than 79.4 dB, and the Noise Efficiency Factor (NEF) is 2.7.
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