A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator

Abstract

The Internet of Things (IoT) is widely predicted to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). Energy efficiency is a huge challenge here, followed by node cost and ease of software (SW) development. Addressing all of the above, this paper presents an 11.7 pJ/cycle subthreshold ARM Cortex-M0+ WSN processing subsystem implemented in low-leakage 65 nm CMOS. Voltage and frequency scalability is from 850 nW active power at 250 mV to 66 MHz above 900 mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80 nW CPU and RAM state-retention power gating for SW transparent leakage reduction. SW and system optimization approaches are described and a $2.94\;\boldsymbol{\upmu}{\text{W}}$ SW ECG workload is presented.