A sub–binary–weighted current calibration technique for a 2.5V 100MS/s 8bit ADC

Abstract

Sub-binary-weighted current circuits make possible low-power and small-area calibration circuits for a low-supply-voltage two-step subranging analog-to-digital converter (ADC). Placed in the calibration circuits, they can be 71% smaller than conventional replica circuits. Moreover, they make it possible to calibrate only one time before A/D conversions, because they can hold the calibrated data during A/D conversions. Consequently, the mean power of calibration circuits can be greatly reduced. The power dissipation of calibration circuits during A/D conversions is only 0.5 mW, and the area is 0.036 mm2, which is 2.3% of the ADC core. The effectiveness of this technique has been demonstrated with a 2.5V 100MS/s 8bit ADC.