A Sub-$\mu$s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support

Abstract

A sub-mus wake-up time power gating technique was developed for low-power SoCs. It uses two types of power switches and a separated power line bypassing rush current to suppress power-supply-voltage fluctuation. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90 nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24 mus , the supply voltage fluctuation was suppressed to 2.5 mV. The area overhead of this technique was less than 1% of the total die area.