A study on the improved programming characteristics of flash memory with Si 3N 4/SiO 2 stacked tunneling dielectric

Abstract

The programming characteristics of memories with different tunneling-layer structures (Si 3N 4, SiO 2 and Si 3N 4/SiO 2 stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO 2/Si 3N 4 stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO 2 or Si 3N 4 for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO 2/Si 3N 4 stacked tunneling layer at V cg = 10 V and V ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10 16–2 × 10 17 cm −3, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.