Abstract
As channel lengths are scaled down to the sub-30nm regime for improved performance and cost per function, the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) would require super-steep doping profiles at the sourcechannel and channel-drain junctions to satisfy parametric constraints. Device architectures that do not have any junctions in the source-channel-drain path will therefore be of interest for scaling to ultra-short channel lengths. The Junction-less transistor, comprised of an isolated ultra-thin highly-doped device layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state, is one such device. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. A key factor determining the effectiveness of such nano-scale devices is their effectiveness as a switch for which the I ON /I OFF ratio is a critical parameter. In this work we have studied the relative sensitivity of the I ON /I OFF ratio to variations in several structural parameters of the device namely channel width, and composition of the dielectric layer, material composition of the channel region (i.e. Si vis-a-vis SiGe), doping concentration of the channel region, non-uniformity in the doping profile etc. We demonstrate through device simulations that replacement of Si with Si-Ge leads to an improvement in performance. The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.
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