Abstract
For 0.18um and 0.13 um technology, Co/TiN deposition process is widely used to form CoSix to provide the needed lower contact resistance of the polysilicon gate. CoSix formation is sensitive to pre-existing wafer surface native oxides and ambient contamination. Pre-clean process before Co film deposition is required to remove residues before Co/TiN deposition. The corresponding chamber RF reflected power too high issue during this pre-clean has significant impact on the etch rate and particle performance. In this paper, three approaches to reduce Co pre-clean chamber RF reflect power are presented.
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