Abstract
Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter effieciency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.
Highlights
Multilevel inverters (MLIs) have been being researched for nearly forty years since the first introduction of three-level neutral-point-clamped (3L NPC) voltage source inverter (VSI) in 1981 1,2
Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the total harmonic distortion (THD) by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8
Simulation and experiment results of 322-SPWM technique are presented in figures from Figure 8 to Figure while those of 322-MOCBPWM technique are illustrated in Figure to Figure 17
Summary
Multilevel inverters (MLIs) have been being researched for nearly forty years since the first introduction of three-level neutral-point-clamped (3L NPC) voltage source inverter (VSI) in 1981 1,2. Compared with traditional two-level VSI (2L VSI), 3L NPC VSI offers a larger number of benefits. Among with many types of 3L NPC topology, 3L T-type NPC (3L TNPC) topology has an advantage in terms of efficiency compared to 3L NPC 5. 3L TNPC VSI possesses higher efficiency in low-voltage applications for the switching frequency between [4-25] kHz such as photovoltaic (PV) system, uninterruptible power supplies (UPSs), and automotive converter system 5,8,9. 3L TNPC VSI combines the benefits of both 2L VSI and 3L NPC VSI, such as lower conduction losses, lower switching losses and higher output power quality 8. The TNPC topology allows the usage of lower voltage rating power switches and offers considerably power losses compared with that of NPC topology [5,8]
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