Abstract
In this paper, we have studied the configuration of direct RF undersampling receiver using a time interleaved ADC (TI-ADC). In the case of higher order undersampling reception, the power levels of spurious due to the timing skew error of TI-ADC become higher than Nyquist sampling reception. We show that by adding an external sample and hold (S/H) IC in front of the TI-ADC, the spurious generated by the timing skew error can be reduced. The experimental result, using 920MHz-band undersampling receiver with 500MHz sampling clock, shows that the proposed configuration (with external S/H IC type) improves the maximum SFDR by 27 dB compared with the conventional one (no external S/H IC type).
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