A study of the specific contact resistance and channel resistivity of amorphous IZO thin film transistors with IZO source–drain metallization

Abstract

We report on the specific contact resistance of interfaces between thin amorphous semiconducting IZO channel layers and IZO source/drain metallization in amorphous oxide thin film transistors (TFTs). As-deposited, low carrier density amorphous IZO layers are difficult to produce and consequently very thin (10–30 nm) channel layers are required for IZO TFT device applications in order to achieve adequately low off-state current. In this article, the transmission line model (TLM) and structures that also serve as IZO gate-down TFTs were used to examine IZO/IZO homojunctions with thin (10 nm) and thick (100 nm) channel layers. Thin, 10 nm, IZO channel devices with IZO source/drain contacts show a threshold voltage of −3.9 V and a very high specific contact resistance (ρC) that varies with gate voltage (VG) in the range 0–10 V from 460 to 130 Ω cm2. Annealing in air at 200 °C resulted in a tenfold improvement in ρC (34 Ω cm2) and corresponds to an increase in carrier density in the channel. Thicker IZO films (100 nm) were too conducting to function as TFTs, but, at zero bias, effective specific contact resistance measured using TLM was 17 Ω cm2 in the as-deposited state and 0.13 Ω cm2 in the annealed state. Corresponding channel resistivity obtained from TLM at VG = 0 V decreased after annealing from 8.2 Ω cm (as-deposited) to 0.3 Ω cm (annealed). The effect of both annealing and positive gate bias is shown to be an increase in carrier density and a corresponding decrease in specific contact resistance.