A Study of Self-Aligned-Via Based All-in-One Etch

Abstract

Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized together with punch-through-via (PTV) scheme for copper interconnect formation since sub-65nm CMOS technology node. In this work, compared to the traditional PTV scheme on sub-45nm test vehicle, we successfully demonstrate that the self-aligned-via (SAV) based all-in-one (AIO) etch process could be fulfilled on thin metal hard-mask and is capable of delivering much better via related TDDB performance without the performance degradation of electromigration (EM), while the contact resistance (Rc) exists different trend with PTV scheme. The high etch selectivity is imperative in both partial via etch, trench etch and liner removal step to reduce the via encroachment on metal hard-mask, the via CD along the unconfined (metal hard-mask) direction should be also optimized to achieve the above desired performance without tiger teeth beneath via bottom. Both via and trench etch recipe need be well optimized to deal with etch stop, via bottom grass and polymer residue issues. Besides, SAV delivers much good yield performance even at misalignment via chain test key, which indicates its very robust overlay margin. But it suffers yield loss at some sub-rule test structure in which trench line end CD is strictly confined by nearby pattern.