Abstract
As CMOS process is advancing towards the high-k/metal gate (HK/MG) technology, dummy poly gate removal (DPGR) process, one of key steps in gate-last technology, poses the challenge for its multiple-film related etching process. Its subsequent photo-resist (PR) strip process is also very difficult due to rigorous process requirements and rather limited wet clean resource. The DPGR process in this work includes two separate DPGR processes for n/p-MOS structures. In the 1st DPGR PR strip process, PR strip capability significantly improves with higher power, higher temperature and higher hydrogen flow-rate. Unlike its PR strip process, post etch treatment (PET) with lower temperature is proven helpful for the 2nd DPGR PR strip. In addition, both bias temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) have been enhanced with the optimized PR strip processes.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
