A study of maximum frequency in FPGA chips using mesh and toroid circuit topologies

Abstract

This paper characterizes the scaling of maximum frequency in lower-performance and higher-performance field-programmable gate-array (FPGA) chips as a function of circuit size and complexity. The evaluation is based on synthesizing mesh and toroid circuit topologies with parameterized node count and interconnect width. Each node accepts two input bit vectors and generates two output bit vectors, and the internal node logic uses either simpler multiplexer-based logic or more complex adder logic. Circuits have been synthesized and results have been compared for the Altera (now Intel) Cyclone IV and Stratix IV families using chips with comparable logic capacity. A smaller collection of synthesis results has also been obtained for Cyclone V and Stratix V chips. The primary interest for the results is to provide, within each chip family, an envelope of performance for different node configurations, interconnect widths, and overall circuit sizes as a reference for actual system implementations. Secondarily, notwithstanding differences in implementation technology, comparing results for Cyclone IV and Stratix IV chips indicates that the maximum frequency for the higher-performance product is between 1.5 and 2.5 times better than the maximum frequency for the lower-performance product, depending on the node/circuit configuration and overall circuit size. Despite some anomalies, a similar range applies when comparing Cyclone V and Stratix V chips.