A study of latch-up hysteresis in n-well CMOS by means of I– V characteristics and photoemission techniques

Abstract

Characterization of latch-up by I– V characteristics as well as by the photoemission technique has been extensively performed on a specially-designed CMOS p- n- p- n structure, furnishing different contact combinations for producing the hysteresis phenomenon of latch-up I– V characteristics. Based on these results, we have concluded that the parasitic lateral resistance of the p + emitter in the n-well is the dominant factor in the formation of the I– V hysteresis. One example in the simplest contact combination has been presented to demonstrate this conclusion. In this example of hysteresis of the latch-up I– V curve, two active latch-up paths have been located separately using the photoemission technique and thus the corresponding branches of I– V curve have been determined. One latch-up path corresponding to the lower I– V branch has been verified to have the lateral p + emitter resistance in series. The value of such resistance has been extracted by experimentally reproducing the lower I– V curve and has been shown to agree closely with that obtained independently from the p + emitter. The hysteresis phenomenon in the latch-up I– V characteristics has been found to disappear after decreasing critically or eliminating this resistance by making the remaining p + emitter contacts partially or totally connected to the power supply. A latch-up equivalent circuit drawn from the experimental results have been proposed to reasonably interpret the anomalous observations.