Abstract
The results of the design and examination of the low-voltage 4H-SIC drift step recovery diode (DSRD) are presented. The study was carried out by simulation in Synopsys Sentaurus TCAD in two-dimensional approach. It is shown that for a low-voltage DSRD an optimization of the doping profile in base region and p+-emitter thickening is essential. For the first time the possibility of a low-voltage 4H-SiC DSRD subnanosecond switching is demonstrated by shaping an impulse of 60 V amplitude with 20 ps rise time on a 50Ω load.
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