Abstract
A Study of 2D Assist Feature Placement
Highlights
Since the CMOS technology entered nanometer era, FinFET has become the mainstream technology of device scaling. 5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries
Extreme UltraViolet (EUV) lithography is a promising technology considered for exposure of 36 nm pitch and below
All of our study is based on the 3D process simulation results with Synopsys software Sentaurus Process Explorer, and the recommendation will be a reference for the process development of 5 nm logic technology
Summary
Since the CMOS technology entered nanometer era, FinFET has become the mainstream technology of device scaling. 5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. With the continuous pattern pitch shrinking, especially into the 5 nm node, the challenge to the process becomes more and more severe. The multiple patterning technology with 193 immersion lithography become too tedious and uncontrollable since it may require 5 or 6 exposures for a single layer for 5 nm technology node. Extreme UltraViolet (EUV) lithography is a promising technology considered for exposure of 36 nm pitch and below. It can produce small patterns with single exposure and simplify the process flow significantly. With the application of EUV technology at the 5 nm node, the process challenges of key process loops will be changed and the traditional process approaches may not fit the new technology conditions. All of our study is based on the 3D process simulation results with Synopsys software Sentaurus Process Explorer, and the recommendation will be a reference for the process development of 5 nm logic technology
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