A study and comparative analysis of low power hybrid-CMOS 1-bit full adders in deep-submicron technology

Abstract

In this paper, a review study and analysis of 1-bit full adder designs is presented with different logic styles such as Hybrid pass logic with static CMOS (HPSC), Hybrid and Hybrid-CMOS. Different styles of logic structures are used to design hybrid-CMOS namely pass transistor logic, complementary pass transistor logic (CPL), swing restoration CPL (SR-CPL) etc. So far the hybrid logic style provides a higher degree of freedom for researcher and designer to target manifold applications. All the full adder circuits have been designed in CADENCE Virtuoso environment at 45nm technology and comparison is done based on various performance parameters such as power dissipation, delay, noise margin and Power-delay product (PDP).