A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters

Abstract

This paper presents a strategy for synthesizing analog cascaded filters with optimal test point insertion. The strategy is based on the implementation of a selective divide-and-conquer approach that permits to ensure high fault detection capabilities while limiting DFT penalties and reducing test time. The proposed solution relies on the evaluation of the filter testability at the different inputs and outputs of the cascaded blocks in order to add DFT only when this testability is not sufficient. Efficient testability evaluation is provided through high-level fault modeling and simulation.