A statistical error-compensated Booth multipliers and its DCT applications

Abstract

In this paper a statistical error compensation (SEC) method for fixed-width Booth multipliers is proposed. According to the statistical simulation for the truncation part, the adaptive compensated biases based on the truncated factors for different bit-width compensated circuit are made up. For the 8×8 fixed-width Booth multiplier as an example, the proposed method achieves higher accuracy comparison with previous works under the same area cost. Furthermore, the proposed SEC Booth multiplier is implemented in two-dimensional (2-D) discrete cosine transform (DCT). Compared to traditional Booth multiplier's applications, the proposed 2-D DCT core can reduce 22% area cost with almost 2 dB peak signal-to-noise ratio (PSNR) penalty. Therefore, the proposed multiplier has a low hardware cost achieving high accuracy designs.