Abstract
A 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip) is described. The linear sum code (LSC)-based ECCRAM is capable of correcting error at any addressed bit as long as there are no more than two errors in the 17 b (the logical row and column) associated with that addressed bit. Test results show that significantly larger error-recovery capability is present in the ECCRAM chip compared to memory chips without error correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with a 3- mu m feature size.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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