A static magnetic memory system for the ENIAC

Abstract

A parallel static magnetic memory system was designed to increase by 100 words the fast access-time memory capacity of the ENIAC. At present the ENIAC has only 20 words of internal memory, in the form of electronic accumulators. This small memory capacity limits the size of the problem that can be programmed without repeated reference to the external punched-card memory. The addition of 100 words to the memory capacity will not only enhance the ease of programming problems for the ENIAC but will also increase the over-all speed of computation by reducing the number of references to the slower access-time magnetic drum memory system. Magnetic memory devices have been under development in a number of laboratories throughout the country for more than three years. At the Harvard Computation Laboratory magnetic shift registers that use rectangular hysteresis-loop magnetic materials have been developed. Their new Mark IV Computer contains 200 words of these magnetic shift register memories. The Digital Computer Laboratory of MIT, and more recently the Research Laboratories of RCA, have investigated static magnetic memory systems of the coincidence-current type. In November 1951 the Ballistics Research Laboratory of the Aberdeen Proving Ground requested the delivery of a static magnetic memory system for the ENIAC. The time schedule implied that the system had to be designed from proven techniques, thus eliminating the possibility of extensive laboratory development. In addition, the peripheral electronics required for code conversion and control imposed other conditions on the system that further limited the freedom of design. One system that had already been demonstrated in our laboratory was well suited to the ENIAC requirements, and although not the optimum in magnetic memories, could be applied immediately to the problem. This system has the following distinctive characteristics: (1) It utlizes one magnetic core with two windings and one germanium diode per bit of memory. (2) The magnetizing force applied to a core is always of sufficient magnitude to switch the core, that is, the system is not amplitude-sensitive. (3) Information is stored in and extracted from the matrix memory in parallel. (4) Read-out is inherently destructive, but the data is immediately restored to the core matrix by the associated electronics. (5) No power is needed to hold information in the cores, and information is not lost in case of power failure. (6) It operates at pulse repetition rates from push button to 125 kilocycles per second, therefore it can provide an excellent speed match or buffer between systems. This paper will be presented in three parts: (1) A description of the basic memory matrix and a description of how data is stored and extracted. (2) A review of the experimental results of a four by four matrix memory. (3) The system as designed for the ENIAC, and some of its construction features.