A standby current limited performance figure of merit for deep sub-micron CMOS

Abstract

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM/sub max/. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM/sub max/ technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM/sub max/ methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM/sub max/. The value of gate length at which FOM/sub max/ occurs decreases with decreasing supply voltage. FOM/sub max/ analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm.