A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme

Abstract

The logic operating voltage is required to suppress for the battery-operated slow application, while the minimum operating voltage of SRAM increase due to the increase in the random threshold-voltage (Vt) fluctuation of the cell transistor (Tr) and the memory capacitance embedded in SoCs with scaling. To suppress the random Vt fluctuation and to guarantee the stable operation over the large memory capacitance at low voltage, a reduced-Vt (LVt) SRAM cell has been proposed. The random Vt fluctuation was suppressed by the proposed LVt cell (Vt = 150 mV) and increase the static noise margin (SNM) for the data-retention at low voltage compared with conventional higher Vt cell (Vt = 300 mV). Another unique disturb-free biasing scheme has also been proposed to cancel the substantial trade-off relationship between SNM and the write margin (WRTM) of SRAM cell. With a 45-nm CMOS technology, these proposed techniques improved the SNM over 6-sigma random Vt fluctuation with the 0.5-V data-retention voltage and the 0.7-V logic bias voltage. Operating current was reduced by 31% at 32-Kbit SRAM module.