Abstract
The commonly used hardware verification languages, such as SystemVerilog have explicit coverage constructs which entitle verification engineers the power to model the function of design into coverage requirement. Verification Engineers usually subtract the functional coverage from their knowledge of the design requirements and map them into coverage points which can be expressed by hardware verification languages. However due to the limitation of syntax of these hardware verification languages, it is very hard in a reasonable way to specify the coverage points for the kind of module whose output is decided by scale-size relationship of its inputs. This paper presents a workaround to analyze the total effective scenarios for this kind of module. The paper also provides a method on how to model these effective scenarios with current syntax of hardware verification language.
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