A special purpose formal verifier for systolic designs in DSP applications

Abstract

In verifying the design correctness of a specific class of architecture, special purpose formal design verifier has the advantage of being able to exploit the attributes of that architecture class to produce efficiency in the design verification process. Such development is important due to the fact that architecture design verification using general purpose theorem prover is usually extremely time consuming. This paper briefly presents the techniques and a Prolog-based verifier VSTA that we developed for formal design verification of systolic array architectures in DSP applications. Systolic architecture has been a popular class of parallel architecture due to its suitability for VLSI implementation. The techniques developed are discussed and a formalism (STA) developed for specifying and verifying systolic designs is reviewed. The strategies and notation adopted exploit systolic attributes for fast design verifications. We develop a Prolog-based verifier to automate our techniques due to Prolog's powerful pattern matching and automatic back-tracking mechanism, its popularity and quality, its similarity in representing facts with STA, and its wide acceptance for lower level module and circuit verification (so as to achieve multilevel reasoning later). In the paper, we also describe the application for our tool to verify the correctness of two systolic array designs. Executing the verifier on our workstation shows that a typical array design can usually be verified in less than 10 minutes.