Abstract
This paper presents a high-speed sample-and-hold circuit (SHC) for very fast signal analysis. Spatial sampling techniques are exploited with CMOS transmission lines in a 0.13 μm standard CMOS process. The SHC includes on chip coplanar waveguides for signal and clock pulse transmission, a clock pulse generator, and three elementary samplers periodically (L = 7.2 mm) placed along the signal propagation line. The SHC samples at 13.3 Gs/s. The circuit occupies an area of 1660 μm × 820 μm and consumes ~6 mW at a supply voltage of 1.2 V. The obtained input bandwidth is ~11.5 GHz.
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