A Spatial ALD Oxide Passivation Module in an All-Spatial Etch-Passivation Cluster Concept

Abstract

Conventional Atomic Layer Deposition (ALD) is also a cycled process, with the extra benefit of the half-reactions being self-limiting, thus enabling layer-by-layer growth. A major obstacle holding ALD from large-scale, high-throughput manufacturing has been the very low deposition rate. This was overcome only recently by introducing the spatial atmospheric-pressure version 1]. Today, spatial ALD is used commercially by the solar industry, and soon other application domains will follow. Shallow and deep plasma etching with nanoscale accuracy is also increasingly based on alternating half-cycles of a directional etch and an isotropic deposition of a passivating polymer layer (usually fluorocarbon or oxyfluoride). Also here the process rates are slow, and to speed up atomic precision etching we conceived a spatially-divided concept as well [2,3]. The process is converted from time- into spatially separated by inserting inert gas-bearing ‘curtains’ of heights down to ~100 μm that confine the reactive gases to individual injection slots in a gas injector head. By moving substrates back and forth under the head one accomplishes the alternate etch/ passivation cycles without idle times needed for switching pressure or purging. The pressure settings range from low-pressure for etching to (sub)atmospheric for passivation, and can be optimized for each separate process zone thus maximizing the total etch rate. A further improvement towards an all-spatial etch approach is in the passivation cycle where the conventional polymer passivation layer is replaced by a spatial atmospheric-pressure ALD-grown oxide passivation layer; see Fig. 1). We have conducted both thermal ALD of Al2O3 at 200 oC and plasma-enhanced SiO2 ALD at 50 oC in pre-etched high aspect ratio trenches (65 nm width and 9 μm depth) in a rotary spatial atmospheric-pressure reactor, and showed - with non-optimized processing and equipment - step conformality values of ³ 80 % for the Al2O3 and 70 % for the SiO2 which is sufficient for most passivations. We conducted a preliminary etch/ALD oxide passivation/etch cycle on a Si-sample with a trench-patterned hard SiO2 mask on top. The sample was processed in two separate (non-connected) reactor chambers, each chamber being supplied with a surface Dielectric Barrier Discharge (DBD) micro-plasma source. The following process cycle was carried out: 1) a 1 min. plasma etch step using SF6/O2 on a biased, non-moving Si-substrate in the low-pressure chamber at room temperature, 2) the thermal deposition of an Al2O3 passivation of only 5 monolayers (5 rotations) in the rotary spatial atmospheric pressure ALD reactor described as above, 3) an identical 1 min. plasma etch step in the low-pressure chamber. The cross-sectional etch profile thus obtained (Fig. 2) showed two typical scallops on the trench sidewall, revealing that both directional and lateral etch had been accomplished in a mixed anisotropic/ isotropic regime where as little as 5 monolayers of Al2O3 passivation were sufficient to preserve the shape of the scallop carved out in the first cycle. Another remarkable observation was the flat etch front of the trench bottom. This may be indicative for the robustness of ALD-grown Al2O3 passivation, and desired in atomically smooth precision etching. In continuous etching trench bottoms are often micro-trenched due to ion scattering from the trench sidewalls which results in faster etching of the side corners. We note that these results have been obtained with non-optimized processing and equipment, so we are confident that further optimization will give more improvements and insights. The process variables are manifold: gas concentration, pressure in the etch and passivation chambers, plasma power, substrate voltage biasing, room temperature processing, plasma source-to-substrate distance, passivation with other spatial ALD oxides like SiO2. We conclude by stating that this all-spatial concept, called ALD-enabled RIE, may find industrial use in cost-effective back-end- and front-end-of-line processing, especially in patterning of structures that require minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Besides in CMOS scaling this concept may also become an important option for fast etching of silicon (or III/V) in die dicing, TSV and MEMS processing.