A Source-Synchronous Architecture Using Mode-Division Multiplexing for On-Chip Silicon Photonic Interconnects

Abstract

A source-synchronous interconnect using mode-division multiplexing (MDM) for potential use in on-chip applications is experimentally demonstrated using a 3-mode 750 μm Silicon photonics structure. Results are presented for simultaneous transmission of two data channels on two separate modes (bit error rate < 10−12 at 10 Gb/s) sampled by an optically forwarded clock sent on a third separate mode. Performance assessment of the mode assignment for the clock is presented. The investigation shows that an optimum clock placement is important at wavelengths where modal crosstalk is higher. For example, at 1553 nm, the clock's jitter decreases from 45 ps down to 2.7 ps where the clock is encoded on a mode with high crosstalk (−18.6 dB) to one that has less crosstalk (−28.6 dB). At 1560 nm where modal crosstalk is better, the clock's jitter is 2.6 ps (−27.8 dB crosstalk) and 1.1 ps (−34 dB crosstalk) without and with optimum clock placement, respectively. With proper clock to mode assignment, the optical interconnect becomes functional across an optical bandwidth of 11 nm enabling MDM–wavelength-division multiplexing architectures.