A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection

Abstract

Non-Maximum Suppression (NMS) algorithm is an important post-processing step in object detection networks for various applications [1]. Standard NMS procedure suffers from poor time complexity and large power consumption due to its iterative and greedy search procedure, making it a bottleneck for object detection networks implemented on various processors [2], [3]. Previous NMS accelerators achieved optimization by stacking arithmetic logical units or computing consecutive iterations simultaneously [4] –[6]. However, several challenges exist, as shown in Fig. 1. First, the highly iterative process of NMS will either cause a high time or space complexity if the hardware resources are not designed properly. Second, the standard NMS process requires sorting of the bounding boxes by the score, and such sorting circuits occupy abundant resources and produce massive data movements. Finally, the Intersection Over Union (IOU) calculation requires hardware unfriendly operations like multiplication and division, taking up loads of valuable hardware resources such as DSPs.