A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA

Abstract

Convolutional Neural Network (CNN) is a very popular method in recent times to solve many computer vision tasks. However, CNN is becoming computationally intensive as time is progressing which requires a dedicated hardware for real time implementation. Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA) are two hot choices to execute and accelerate the CNN network. FPGA has an advantage over GPU due to its flexible architecture and it can also provide high performance per unit watt of power. These benefits make FPGA a suitable candidate for CNN acceleration. However, optimization is required for FPGA based accelerator design to accommodate more computations. One of the challenges in accelerator design is to perform addition of intermediate results generated in a process of convolution. Therefore, Multi-Operand Adders (MOAs) are necessary in the accelerator design of CNN on FPGA but consume most of the area. Optimization strategy based on WALLACE tree architecture is proposed in this article to replace the typical binary adder tree in CNN accelerator design. Experimental results show an improvement in terms of area optimization and performance in comparison with the previous implementation.