Abstract
A mathematical formulation of the problem is presented using the concepts and terminology of graph theory. This formulation includes both stages of the placement problem wherein the vertices of the circuit graph are partitioned into several subsets (representing integrated circuit packages) which are, in turn, assigned to geometric positions corresponding to the printed circuit board specifications. Utilizing the manhattan metric, a heuristic procedure is described which provides minimum length placements on two-sided printed circuit boards consistent with the requirements of PC board designers. Computational results from problems arising in actual design efforts are discussed.
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