A Soft-Error Hardened by Design Microprocessor Implemented on Bulk 12-nm FinFET CMOS

Abstract

We describe the porting of a soft-error (SE) hardened microprocessor to a modern 12-nm bulk CMOS finFET fabrication process and radiation testing results. The microprocessor includes latch-based cache and main register file (RF) arrays, with compact dual-patterned layouts. It is protected by dual modular redundancy (DMR) in the speculative pipeline, RF, and caches. Self-correcting triple modular redundant (TMR) flip-flops provide fine-grain protection in the TMR circuits that hold key architectural state. The DMR circuits are protected by checking circuits at the caches, RF, and crossovers to the TMR state. In the event of a DMR mismatch, an SE exception is taken, and the machine state is repaired via software. This approach also allows the detailed machine state reporting to elucidate the SE root cause circuits and cross sections. Broad beam radiation testing shows that it responds correctly to detected SEs. The by-circuit cross sections of the various circuits are reported for both heavy ions and protons.