A soft error mitigation technique for constrained gate-level designs

Abstract

A single event transient generated from a high-energy particle is capable of corrupting the status of a digital system. Not only in aerospace engineering, but even in terrestrial application system reliability is expected to worsen due to radiation effects as semi-conductor technology advances. In this paper, we introduce an incremental gate-sizing method for minimizing soft errors in gate-level designs. The target designs have constraints for marginal circuit area and path delay. The proposed heuristic algorithm searches for each driving strength of logic gates using modified topological order. It gives a more effective solution in large marginal constraints than the existing greedy approach. In the experiments, we show the effectiveness of our algorithm using several benchmark circuits synthesized by a 130nm cell library.