A Soft Error Detection and Recovery Flip-Flop for Aggressive Designs With High-Performance

Abstract

Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits, we proposed a radiation hardened flip-flop in this paper, namely, Soft Error Detection and Recovery flip-flop (SEDR-FF). Error detection is based on delayed sampling and redundant storage by a redundant latch. A pulsed clock is adopted to control the redundant latch to reduce the hold time constraint of the latch. To generate the pulsed clock, two efficient delay elements are presented in this paper. Error recovery is accomplished by reloading the previous data stored in a history latch. Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU. It has low overhead of setup time, and is suitable for high-performance designs. In addition, compared with other radiation hardened cells, the proposed flip-flop has moderate power and area overhead, and has lower area cost for fixing hold time violations in circuits designs.