A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA

Abstract

Until now, logic simulators are still the most popular verification tools. Although they can provide full controllability and observability during the verification process, the simulation speed is too slow for large amounts of input patterns. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug using this approach due to poor visibility in FPGAs. Therefore, in this paper, we propose another approach to record the internal behaviors of a FPGA and replay the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in FPGA. Moreover, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.