Abstract
In this paper, the effect of current control loop on the grid synchronization is analyzed for a three phase SiC filterless PV inverter. A small signal model is proposed to represent the effect of current control loop on the phase locked loop (PLL). Analysis shows that, subharmonic oscillation can happen under conventional PLL design method. This is because the current control loop behaves as an additional feedforward term to the PLL. This effect is not considered in conventional PLL design. Experiments are performed on a 100-kVA three phase SiC filterless inverter prototype that connected to 17x weak grid. The results validate the analysis and the effectiveness of proposed design. Although the proposed analysis and design is targeting the filter-less VSCs, it can also be applied to conventional VSCs that connected to a very weak grid.
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