Abstract
Sinusoidal signal generators (SSG) are increasingly required for on-chip integration in impedance measurement architectures for bio-sensing and chemical sensing applications. For digital SSG architectures, there are inherent trade-offs among circuit area, power, and linearity. In this work, we present a new approach that encodes a delta-sigma-modulated look-up table (ΔΣM-LUT) to decrease digital circuit size and power while maintaining high linearity. In addition, we present a method for analyzing the combined periodicity of the modulator and the LUT for adding dither to further improve performance. The approach is demonstrated using a 5-bit, 2nd-order ΔΣM-LUT controlling a digital ΔΣ modulated SSG, where it enables a significant decrease in digital circuit area and power compared to state-of-the-art designs while achieving 64.6 dBc SFDR and 0.074% THD.
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