Abstract
This paper describes the design of a high performance Si-Gate CMOS LSI circuit for an Adaptive Delta Modulation System (ADM). The circuit design is based on 4 μ design rules. The size of the die is approximately 25 mm 2 and the circuit operates synchronously under the control of an 8 MHz two phase non-overlapping clock. A fault tolerant scheme is used at the comparator section for reliability improvement purposes. The adaptation logic of the system is based on the algorithm introduced in [2] where a rigorous proof is provided for showing the optimality of the algorithm in terms of performance. This paper demonstrates the feasibility of implementing this algorithm with a single chip adaptive delta modulator.
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