Abstract
In this paper, we present a single-chip receiver for DVB data broadcasting system, which is designed using the methodology of hardware and software co-design. The hardware part filters out and descrambles the necessary MPEG-2 transport stream (TS) packets, then sends them to PC. Some useful peripheral functions such as PCI interface, I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> C bus controller and smart card 7816 interface are also developed to provide a cost-effective solution. Meanwhile, multi-protocol decapsulation related to data broadcasting protocol is analyzed and implemented mainly by software. In order to improve the throughput and hardware utilization, we adopt chaining mode direct memory access (DMA) scheme and a double buffer approach both in hardware and in software. Moreover, the parameters of chaining mode DMA and the depth of buffer are further optimized by theoretical analysis. The result indicates the throughput of chaining mode DMA is up to 475.8 Mb/s, which is 24 times as much as non-chaining mode DMA strategy
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