Abstract
Multicore is quickly becoming the norm, even in the embedded world. This trend is thought to be sustained as long as the progress of micro-electronics will permit, by regularly doubling the number of available computing cores on a given chip. That means that multicore aware programs are no longer an option, but at the same time, parallel programming is still very hard nowadays despite progresses in parallel languages. From these observations, we investigated how to use multicore in a fashion that would be as close as possible as single processor programming, at least from the program design and debug point of view, by a kind of generalization of the superscalar design. One of the aim is also to guarantee little latency and synchronization overheads: for that a loose synchronization mechanism called “weak synchronization” is described. It is supported by a hardware/OS co-design. Some first evaluations of the system performance are provided.
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